The present invention relates to a semiconductor device and a method of fabricating tho came.
In conventional semiconductor devices, impurity diffusion layers, gates, and contact holes, and so on are formed in a surface portion of a flat semiconductor substrate by using resist patterns. FIG. 1 shows the sectional structure of a conventional MOS transistor. A drain 62 and a source 63 each made of an n-type impurity diffusion layer are formed at a predetermined interval in a surface portion of a flat p-type semiconductor substrate 61. A gate electrode 65 is formed on the resultant surface via a gate oxide film 64 to form an n-channel fOS transistor 66. In this conventional semiconductor device, however, the size of a fabricable transistor is unavoidably larger than the minimum processing size F corresponding to the limits of photolithography; generally, a size of 2F is necessary. For this reason, it is conventionally impossible to unlimitedly increase the degree of integration.
In conventional semiconductor devices as described above, elements are formed on the surface of a flat semiconductor substrate, and this requires a size larger than the minimum processing size F. So, the degree of integration cannot be increased.
Also, semiconductor memories have greatly improved with the recent micropatterning. However, straightforward development of conventional technology is against the trend to reduce a power consumption required by a high integration degree of LSIS. For example, in a non-volatile memory device, if an operating voltage was reduced with the reliability of a tunnel oxide film kept high, the efficiency of injection of electrons into a floating gate decreases.
For example, letting F be the minimum processing size in state-of-the-art general nonvolatile semiconductor memories, an element area of about 5.5F.sup.2 is necessary even for a cell with the simplest cell structure and the minimum cell area. To write data by injecting electrons into the floating gate or erase data by extracting injected electrons from the floating gate of even a cell of this size, a very high electric field of, e.g., 18 V must be applied to cause FN tunneling in the tunnel oxide film.
Additionally, a strong electric field is applied not only to the tunnel oxide film between the substrate and the floating gate but also to an insulating film between the floating gate and the control gate. Therefore, to allow a tunnel current to flow only through the tunnel oxide film to make efficient data write or erase possible, the ratio of the thickness of the tunnel oxide film to that of the insulating film is adjusted to decrease the capacitive coupling ratio .gamma.(=C1/C2) of the capacitance C2 of the tunnel oxide film to the capacitance C1 of the insulating film. However, even when this is performed, the maximum operating voltage is still high, about 18 V, when data is written in or erased from conventional semiconductor memories.
On the other hand, in devices whose maximum operating voltage is as low as 12 V, the voltage required to write or erase data is decreased by using, e.g., channel hot electron injection. This, however, complicates the cell structure and takes the cell area very large, 11.5F.sup.2.
As described above, no conventional semiconductor memories can reduce the cell area and the maximum operating voltage at the same time.